None of the “pico” DLP solutions support anything but 1D vertical keystone.
So it could certainly have been an “hardware” feature, but it would have been in the input/HDMI scaling stage (a different chipset, since this one doesn’t appear to have it), or it would have required additional processing hardware before the TI processing stage.
Like it has been said, I agree lens shifting optics are out of reach for this class of device/price.
https://www.jstage.jst.go.jp/article/elex/7/5/7_5_346/_pdf
I’m wondering what the FPGA utilization of that phat Zynq chip really is. A more constrained implementation that what they describe in the link above wouldn’t be completely unreasonable. That would eliminate the need for yet another FPGA in between the scaler and the DLPC+FPGA in the DMD chipset. Maybe this was the idea from the beginning but it wasn’t feasible for some reason?
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